This invention relates to interrupt processing and task switching circuitry and methods in data processing systems.
Modern computers use special hardware to automate interrupt processing and task switching. Interrupts include such events as I/O transfers, clocks, hardware faults, software interrupts and software faults such as divide by zero. So that the interrupting program does not alter the running program, all states of the interrupted task must be saved. Then, all of the new interrupting task states must be retrieved from memory and the processing then continued with these new interrupting task states. Once the interrupting task is completed, a Return From Interrupt instruction is usually executed causing the state save process to reverse itself and restore the previous task.
Most modern computers achieve the task change process using a hardware interrupt mechanism that first disables additional interrupts and saves only the minimum number of state registers before jumping to a special interrupt service program. The special interrupt service program then saves the rest of the task registers as may be required. It then loads the register for the interrupting tasks. This process is reversed for returning from interrupts so that the computer may then return to its original task.
During the saving and restoring of the registers, any further attempted interrupts must be disabled to prevent corruption of the system's existing data. Thus, the computer is insensitive to interrupts for these periods of time, known as interrupt latency. Traditional computer architectures must complete current instructions before responding to interrupts. Typically, these instructions vary widely in their durations. In addition, various computer architectures have different interrupt latencies depending upon the modes of the currently executing process and that of the interrupting process. These two factors combine to cause highly non-deterministic interrupt latency delays and overhead.
Besides the latency delay associated with beginning each new interrupt task, in state-of-the-art computers there is also the time spent switching between tasks. This switching time is the interrupt and task change processing overhead. It is the time used for saving and restoring the registers, and thus is time unavailable for use in processing. This interrupt and task change processing overhead amounts to tens or hundreds of cycles in many modern computers. Even at multi-Megahertz clock rates, the combination of both the latency delay and the time required with respect to switching overhead results in computers that can only process interrupts at tens or hundreds of Kilohertz. Meanwhile, multimedia data transfers take place at tens to hundreds of megahertz.
As a result of these modern computer time limitations in interrupt and task change latency and processing overhead, current computers cannot handle the required data rates without the use of extensive storage buffers and auxiliary specialized processors. The size of these buffers causes multimedia systems to span dozens of chips, each with its additional attendant cost. Even as technological advances place more memory on each integrated circuit, the large size and complexity of current buffered data transfer methods continue to cause excess manufacturing costs while decreasing computer operational performances. Modern applications require an ever greater number of interrupts which simply further aggravates the problem.
Multiple register interrupt and task switch systems have been proposed before, but all have suffered various limitations. In particular, the use of large register sets causes a concomitant increase in wiring and capacitance related delays, slowing down the entire computer. Other methods have used separate register stores for data storage, but this results in a waste of time during the course of the movement of the data to and from these task saving registers before the execution of an interrupt. Then, additional time must be used to load the working data into the general purpose registers before interrupt processing can begin.
A further disadvantage of conventional computer architectures is that they do not incorporate effective methods for tracing processor flow, including task changes, without expensive hardware emulators and logic analyzers. Meanwhile, conventional hardware emulators cannot test computers under actual operational conditions as they cannot run as fast as the computers that they are testing.
Also, computers lack hardware based task linking sequential execution systems and deadline priority “impatience” counters to permit interrupts to automatically increase their priorities with the passage of time.
Meanwhile, multicycle uninterruptable instructions also increase interrupt latency delays. These latency delays can be hundreds or even thousands of cycles long in modern complex computers.
Furthermore, current state-of-the-art CPU's pipeline the processing of data and instructions in order that more data and instructions can be processed in each cycle. This has a number of disadvantages. Whenever an interrupt comes in, the pipeline CPU must abandon whatever is unfinished in the pipeline, and reset the various counters to resume processing when it restarts. This is called a pipeline “stall”. When a branch instruction is executed, the pipeline CPU must either guess at which way the branch will go, stall or try to follow the multiple, possible branch outcomes. All of these various pipeline CPU situations can cause computers to waste processing resources and result in further delays.
Additionally, conventional computer systems require extensive buffering to accommodate high data rates. Therefore, they are not generally as suitable for single-chip, unitary construction fabrication with its advantages in terms of costs, lower energy and cooling expenditures and increased performances.